? 2003 by eureka technology inc. 4962 el camino real, los altos, ca 94022, usa tel: 1 650 960 3800 fax: 1 650 960 3805 http://www.eurekatech.com page 1 eureka technology ? fully supports powerpc? 60x bus protocol, include powerpc 603, 604, 740, 750 and 8260. ? automatic bus arbitration for address bus and data bus based on internal bus request. ? separate address bus and data bus tenure with individual grant signals. ? supports address bus retry and data transfer error. ? qualified address bus grant and data bus grant through the use of bus busy sig- nals. ? user specified burst data transfer and single beat data transfer. ? supports two back-end user request ports with built-in arbitration. ? efficient back-end bus for internal data transfer. ? supports bus parking. ? designed for asic or programmable logic device implementations in various system environments. ? fully static design with edge triggered flip-flops. ? optimized for actel sx-a, rtsx-s, ax, and apa product families. EP201 powerpc bus master features address retry restart product summary powerpc host bus data tenure address tenure arbitration logic for user bus dual user interface
? 2003 by eureka technology inc. 4962 el camino real, los altos, ca 94022, usa tel: 1 650 960 3800 fax: 1 650 960 3805 http://www.eurekatech.com page 2 eureka technology the powerpc bus master is a bus interface unit designed for the powerpc host bus. it allows the user to initiate data transfer directly on the powerpc cpu bus through a very simple user interface. the powerpc bus master arbitrates for the powerpc address bus before starting any transfers. it handles separate address and data bus tenure so that data bus is arbitrated independently from the address bus. the bus master handles address retry by the cpu or other sources on the cpu bus. upon address retry, it automat- ically re-starts the data transfer unless an error has occurred. single beat, burst data and extended mpc8260 data transfer are supported. differ- ent data size and transfer types are allowed and can be specified through an inter- nal back-end bus. there are two user interface ports provided by the bus master. it allows two different devices to access the powerpc bus through a single bus mas- ter. the bus master contains arbitration logic to arbitrate between the two request ports. the following table summarizes the optional features which can be provided with the core as required by user application. options description extended data transfer mpc8260 extended data transfer dual or single user interface supports one, two or multiple user request ports. address only transfer execute address only transfer on the cpu bus for data snooping. family device utilization performance (-speed grade) seq comb total ram proasicplus apa150-std 452 882 22% 40mhz axcelerator ax500-3 408 290 9% 126mhz rtsx-s rt54sx32s-2 410 281 24% 61mhz optional features EP201 powerpc bus master actel device utilization data descriptions
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